In a world of Computerised intelligence taking jobs away from Humans, people look for control and exercise as does a retired person.

For some years I have lived on Benefits and have wondered of about finding a hobby school to help with control and exercise of myself.

I found an 8 bit computer called the 1802, and there is a hobby group as well.

It is good for learning Electronics and in my case the Antenna that I want to put with the 1802,

is big enough to be able to do some physical exercises on, if I do ever finish building it.

It is also called the RCA COSMAC PDP 1802.

RCA means the Radio Corporation of America, now mostly non existent.

COSMAC means Complementary Symmetry Monolithic Array Computer,

Complementary is something to do with CMOS, which means Complementary Metal Oxide Silicon,

where there is 2  MOS transistors, 1 for pulling up to the +ve voltage and the other for pulling down to the 0 volts,

and the Computer was for the first time on a single piece of Silicon,

and Silicon is what stone is made of, and Lith means stone, and the rest I still do not yet know.

CDP means perhaps COSMAC Development Package perhaps?

It has 16 R registers of 16 Bits for general use.

It has a D register of 8 Bits for temporary Data.

It has a DF register of 1 Bit for Carry or Borrow indication.

It has a P register of 4 Bits for setting which R register is the Program Counter.

It has a X register of 4 Bits for setting which R register is the Program Counter.

It has a T register of 8 Bits for storing the P register and X register during an Interrupt.

It has a Q register of 1 Bits often for setting an LED on or off.

It has an IE register of 1 Bits for setting and un setting Interrupt Enable during an Interrupt.

It has a Q register of 1 Bits often for setting an LED on or off, which is also one of the 4 outputs.

The 4 Bit N register holds the low order 4 Bits of the Instruction Byte.

The 4 Bit I register holds the high order 4 Bits of the Instruction Byte.

The outputs of the 1802 chip and the inputs, are much more in evidence, than the 6502, as with the 6502 3 of the pins were not connected, and 16 instead of 8 on the 1802, were used for addressing memory.

The 1802 is seemingly more beginner friendly than the 6502.

In the Microtutor 2 Manual,

thre is on page 8, a 4 Byte program:

0000 E2,  0001 27,  0002 51,  0003 F6,

on page 8 it does not explain what it is,

but I want to do some guessing

to see if I can learn how to program a 1802 using the Hexadecimal numbers:

THE E2 IS A 1 BYTE INSTRUCTION, THAT SETS THE PROGRAM COUNTER REGISTER NUMBER OF THE 16 GENERAL PURPOSE REGISTERS, AND EACH ONE HAS 2 BYTES, MAKING 16 BITS.

SO E2 IS SAYING THAT GENERAL PURPOSE REGISTER NUMBER 2 OR 0010 IS IT.

THE 27 IS A 1 BYTE INSTRUCTION, THAT REDUCES BY 1 THE 16 BIT NUMBER AT REG 7.

THE 51 IS A 1 BYTE INSTRUCTION, MOVES THE BYTE OF D REGISTER, TO THE MEMORY LOCATION, THAT IS AT THE ADDRESS, NAMED BY THE NUMBER STORED IN REGISTER 1.

THE F6 IS A 1 BYTE INSTRUCTION, THAT SHIFTS THE BIT PATTERN OF IN THE D REGISTER,

BY 1 TO THE RIGHT, PLUS THE FOLLOWING ALSO HAPPENS:

THE LEAST SIGNIFICANT BIT OF THE D REGISTER CALLED B0, GOES TO THE DF REGISTER, WHICH IS THE 1 BIT ALU CARRY REGISTER. THE MOST SIGNIFICANT BIT OF THE D REGISTER CALLED BF [I THINK IT IS CALLED BF OR MAYBE B15] HAS A 0 PUT IN IT.

MY CONCLUSION IS THAT THIS IS NOT A PROGRAM THAT DOES A USFULL THING, AND THAT IT IS ONLY AN EXAMPLE PROGRAM.

The next Program is on page 9:

0000 E1, 0001 F8, 0002 FF, 0003 A1, 0004 FC, 0005 01, 0006 51, 0007 64

0000 E1 SETS X AS 0001 MAKING REGISTER 1 AS THE PROGRAME COUNTER.

0001 F8 MOVES THE NEXT BYTE FF INTO THE D REGISTER.

0002 FF AS ABOVE.

0003 A1 MOVES WHAT IS IN D TO REGISTER 1, IN THE LEAST SIGNICANT SIDE.

0004 FC ADDS THE NEXT BYTE 01 TO D, AND THEN RESULT TO D, WITH CARRY TO DF. 0005 01 AS ABOVE.

0006 51 MOVES THE BYTE OF D REGISTER, TO THE MEMORY LOCATION, THAT IS AT THE ADDRESS, NAMED BY THE NUMBER STORED IN REGISTER 1.

0007 64 AN OUTPUT OPERATION WHICH MOVES TO THE DISPLAY, THE BYTE FROM MEMORY THAT IS AT THE ADDRESS THAT IS IN THE REGISTER THAT THE REGISTER X IS POINTING AT, MAKING THAT THE PROGRAM COUNTER REGISTER AND AND THE REGISTER IS INCREASED BY 1.

THIS IS A 4N CODE!]

0008 21 THE NUMBER IN REGISTER 1 IS REDUCED BY 1.

0009 3F SHORT BRANCH TO 09 IF E4 IS 0

000A 09 AS ABOVE.

000B 37 SHORT BRANCH TO 0B IF E4 IS 1

000C 0B AS ABOVE

000D F0 THE BYTE AT THE MEMORY THAT THE GENERAL REGISTER POINTS TO,

          THAT IS THE REGISTER POINTED TO BY THE X REGISTER THAT USUALLY IS THE                PROGRAM REGISTER.

000E 30 SHORT BRANCH TO 04

000F 04 AS ABOVE

Seems more likely to do something, but not sure yet.

The next program is on page 11:

0000 E1 EN  N THRU TO X, THIS IS CALLED SEX. sets the data X register as R1.

0001 F8KK  KK THRU TO D, THIS IS CALLED LDI. sets the D register as 0F.

0002 0F AS FOR ABOVE.

0003 A1 AN  D THRU TO RN.0, THIS IS CALLED PLO. 0F is put into the lower bit of  R1.

0004 64  MX THRU TO HEX DISPLAY, RX + 1, THIS IS CALLED OUT 4. what is at R1 is displayed, which is 00.

0005 3FMM  GO TO MM, IF EF4 = 0    IN, THIS IS CALLED BN4. this loop waits at 05.

0006 05 AS FOR ABOVE.

0007 6C  8 BIT SWITCHES THRU TO MX, D, THIS IS CALLED INP 4. 0F has put into it the switches setting.

0008 F8KK  KK THRU TO D, THIS IS CALLED LDI. sets the D register as 0A.

0009 0A AS FOR ABOVE.

000A F7  D - MX THRU TO D, DF, THIS IS CALLED SM. 0A - switch settings thru to D.

000B 51 5N  D THRU TO MN, THIS IS CALLED STR. what is in D is put into the memory location that RN is pointing to.

000C 64  MX THRU TO HEX DISPLAY, RX + 1, THIS IS CALLED OUT 4. what is at R1 is displayed.

000D 30MM  GO TO MM, THIS IS CALLED BR. the program counter R0 has put into it 0D.

000E 0D AS FOR ABOVE.

000F 00  IDLE, THIS IS CALLED IDL.

This one is difficult, because I do not understand the Math in the Games trick.

The next program is on page 12:

0000  7A PUTS  0 THRU TO Q (LIGHT OFF), THIS IS CALLED SEQ.

0001  F8KK  KK THRU TO D, THIS IS CALLED LDI.

0002  10 THIS IS THE KK OF ABOVE.

0003  B1 BN  D THRU TO RN.1, THIS IS CALLED PHI.

0004  21 2N  RN - 1, THIS IS CALLED DEC.

0005  91 9N  RN.1 THRU TO D, THIS IS CALLED GHI.

0006  3A 3AMM  GO TO MM, IF D NOT = 00, THIS IS CALLED BNZ.  *

0007  04 THIS IS THE MM OF ABOVE, AND MAKES ANOTHER DELAY LOOP.

0008  31 31MM  GO TO MM, IF Q = 1, THIS IS CALLED BQ.  *

0009  00 THIS IS THE MM OF ABOVE AND IT IS A TIME DELAY LOOP.

000A  7B 7B  1 THRU TO Q (LIGHT ON), THIS IS CALLED REQ.

000B  30 30MM  GO TO MM, THIS IS CALLED BR.  *

000C  01 THIS IS THE MM OF ABOVE, TO LOOP A PART OF THE PROGRAM.

This one seems to switch the Q light on and off fairly slowly for the Human eye.

A WIRE SPIDER WHOS LEGS CATCH ON SO MANY BITS

I made this list of Instructions with some explanation for:

https://en.wikipedia.org/wiki/RCA_1802

RCA CDP 1802 instructions in Hexadecimal order:

As a list of 92 items, that cover all of the 256 possible two digit Hexadecimal numbers.

Opcode, Instruction, Mnemonic, Machine Cycles.

00 It is idle, doing fetch cycles (I think), IDL, 2 cycles.

0N Load D from address in RN, LDN N, 2 cycles.

1N Increment the 16 bit number in RN, INC N, 2 cycles.

2N Decrement the 16 bit number in RN, DEC N, 2 cycles.

30MM Branch R(P) unconditionally to MM, BR, 2 cycles. *

31MM Branch R(P) to MM if Q is 1, BQ, 2 cycles. *

32MM Branch R(P) to MM if D is 00, BZ, 2 cycles. *

33MM Branch R(P) to MM if DF is 1, BDF, 2 cycles. *

34MM Branch R(P) if the External Flag EF1 is 1, B1, 2 cycles. *

35MM Branch R(P) if the External Flag EF2 is 1, B2, 2 cycles. *

36MM Branch R(P) if the External Flag EF3 is 1, B3, 2 cycles. *

37MM Branch R(P) if the External Flag EF4 is 1, B4, 2 cycles. *

38 Skip R(P) by 1 addressed memory byte, SKP, 2 cycles.

39MM Branch R(P) to MM if Q is 0, BNQ, 2 cycles. *

3AMM Branch R(P) to MM if D is NOT 00, BNZ, 2 cycles. *

3BMM Branch R(P) to MM if DF is 0, BNF, 2 cycles. *

3CMM Branch R(P) if the External Flag EF1 is 0, BN1, 2 cycles. *

3DMM Branch R(P) if the External Flag EF2 is 0, BN2, 2 cycles. *

3EMM Branch R(P) if the External Flag EF3 is 0, BN3, 2 cycles. *

3FMM Branch R(P) if the External Flag EF4 is 0, BN4, 2 cycles. *

4N Load D from address in register RN and advance RN by 1, LDA N, 2 cycles.

5N Store D into memory pointed to by register RN, STR N, 2 cycles.

60 Increment the 16 bit number in R(X), IRX, 2 cycles.

61 Output from memory byte at R(X) to the BUS condition, OUT 1, 2 cycles.

62 Output from memory byte at R(X) to the BUS condition, OUT 2, 2 cycles.

63 Output from memory byte at R(X) to the BUS condition, OUT 3, 2 cycles.

64 Output from memory byte at R(X) to the BUS condition, OUT 4, 2 cycles.

65 Output from memory byte at R(X) to the BUS condition, OUT 5, 2 cycles.

66 Output from memory byte at R(X) to the BUS condition, OUT 6, 2 cycles.

67 Output from memory byte at R(X) to the BUS condition, OUT 7, 2 cycles.

68 (Undefined for the RCA 1802)

69 Input from the BUS condition to the memory byte at R(X) and the D register as well, INP 1, 2 cycles.

6A Input from the BUS condition to the memory byte at R(X) and the D register as well, INP 2, 2 cycles.

6B Input from the BUS condition to the memory byte at R(X) and the D register as well, INP 3, 2 cycles.

6C Input from the BUS condition to the memory byte at R(X) and the D register as well, INP 4, 2 cycles.

6D Input from the BUS condition to the memory byte at R(X) and the D register as well, INP 5, 2 cycles.

6E Input from the BUS condition to the memory byte at R(X) and the D register as well, INP 6, 2 cycles.

6F Input from the BUS condition to the memory byte at R(X) and the D register as well, INP 7, 2 cycles.

70 The memory byte at the address in R(x) is Returned to the memory byte at the address in R(P) after an Interrupt, and the Interrupt Enable register IE is enabled by setting to 1, R(X) is incremented, RET, 2 cycles.

71 The memory byte at the address in R(P) is moved into the memory byte at the address in R(X), Interrupt Enable register IE is Disabled by setting it to 0, R(X) is incremented, DIS, 2 cycles.

72 Load the memory byte at R(X) into the D register, increment R(X), LDXA, 2 cycles.

73 Store the D register into the memory byte at R(X) and decrement R(X), STXD, 2 cycles.

74 Add the memory byte at R(X) to the D register and the carry register DF, and the answer is moved to the D register and the carry register DF, ADC, 2 cycles.

75 Subtract the D register and the carry register DF from the memory byte at R(X), and move the answer to the D register and the carry register DF, SDB, 2 cycles.

76 Shift the D register right and the carry register DF, SHRC, 2 cycles.

77 Subtract the memory byte at R(X) from the D register and the carry register, and move the answer to the D register and the carry register DF, SMB, 2 cycles.

78 Save the byte in register T into the memory byte at R(x), SAV, 2 cycles.

79 Save the 4 bit nibble in register X and the 4 bit nibble in register P into the byte in register T, the byte in register T is moved into the byte in register R(2), the nibble in X is moved into the nibble P, R(2) is decremented, MARK, 2 cycles.

7A Reset Q output to 0, REQ, 2 cycles.

7B Set Q output to 1, SEQ, 2 cycles.

7CKK Add the byte KK to the D register with the carry register DF, move the answer to the D register and the carry register DF immediate, ADCI, 2 cycles.

7DKK Subtract the byte in the D register and the carry register DF from the byte KK, and move the answer to the D register and the carry register DF, immediate 2, SBDI, 2 cycles.

7E Shift the D register left and the carry register DF, SHLC, 2 cycles.

7FKK Subtract the byte KK from the D register and the carry register DF, move the answer to the D register and the carry register DF immediate, SMBI, 2 cycles.

8N Move the low byte of the RN register into the D register, GLO N, 2 cycles.

9N Move high byte of the RN register into the D register, GHI N, 2 cycles.

AN Put the byte in the D register into the low byte of the RN register, PLO N, 2 cycles.

BN Put the byte in the D register into the high byte of the RN register, PHI N, 2 cycles.

C0MMMM Long branch R(P) to MMMM unconditionally, LBR, 3 cycles.

C1MMMM Long branch R(P) to MMMM if Q is 1, LBQ, 3 cycles.

C2MMMM Long branch R(P) to MMMM if D is 00, LBZ, 3 cycles.

C3MMMM Long branch R(P) to MMMM if DF is 1, LBDF, 3 cycles.

C4 No operation, NOP, 3 cycles.

C5 Long skip R(P) by 2 addressed memory bytes if Q is 0, LSNQ, 3 cycles.

C6 Long skip R(P) by 2 addressed memory bytes if D is NOT 00, LSNZ, 3 cycles.

C7 Long skip R(P) by 2 addressed memory bytes if DF is 0, LSNF, 3 cycles.

C8 Long skip R(P) by 2 addressed memory bytes, LSKP, 3 cycles.

C9MMMM Long branch R(P) to MMMM if Q is 0, LBNQ, 3 cycles.

CAMMMM Long branch R(P) to MMMM if D is NOT 00, LBNZ, 3 cycles.

CBMMMM Long branch R(P) to MMMM if DF is 0, LBNF, 3 cycles.

CC Long skip R(P) by 2 addressed memory bytes if the Interrupts Enabled IE is 1, LSIE, 3 cycles.

CD Long skip R(P) by 2 addressed memory bytes if Q is 1, LSQ, 3 cycles.

CE Long skip R(P) by 2 addressed memory bytes if D is 00, LSZ, 3 cycles.

CF Long skip R(P) by 2 addressed memory bytes if DF is 1, LSDF, 3 cycles.

DN Set the nibble in the P register to point to the RN register, SEP N, 2 cycles.

EN Set nibble in the X register to point to the RN register, SEX 0, 2 cycles.

F0 Load the byte in the D register with the memory byte at R(X), LDX, 2 cycles.

F1 Logical OR the byte in the D register with the memory byte at R(X), move the result into the D register OR, 2 cycles.

F2 Logical AND the byte in the D register with the memory byte at R(X), move the result into the D register, AND, 2 cycles.

F3 Exclusive OR the byte in the D register with the memory byte at R(X), move the result into the D register, XOR, 2 cycles.

F4 Add the byte in the D register to the memory byte at R(X), move the result into the D register, 2 cycles.

F5 Subtract the byte in the D register from the memory byte at R(X), move the result into the D register SD, 2 cycles.

F6 Shift the D register right 2, SHR, 2 cycles.

F7 Subtract memory byte at R(X) from the D register, move the result into the D register SM, 2 cycles.

F8KK Load KK into the D register, LDI, 2 cycles.

F9KK OR the byte in the D register with KK, move the answer into the D register, ORI, 2 cycles.

FAKK AND the byte in the D register with KK, move the answer into the D register, ANI, 2 cycles.

FBKK Exclusive OR the byte in the D register with KK, move the answer into the D register, XRI, 2 cycles.

FCKK Add the byte in the D register with KK, move the answer into the D register and the carry register DF, ADI, 2 cycles.

FDKK Subtract the byte in the D register from KK, move the answer into the D register, SDI, 2 cycles.

FE Shift the D register left, SHL, 2 cycles.

FFKK Subtract the byte KK from the D register, move the answer to the D register and the carry register DF, SMI, byte 2 cycles.

* GO to MM in same 256-Byte Page.

Notes:

RN/RX = 16 Bit general PURPOSE register (16 of these labled R0 to RF).

RN.0 Low-order register number

RN.1 High-order register number.

MN/MX Memory Byte location addressed by contents of RN/RX.

It has 16 R registers of 16 Bits for general use.

It has a D register of 8 Bits for temporary Data.

It has a DF register of 1 Bit for Carry or Borrow indication.

It has a P register of 4 Bits for setting which R register is the Program Counter.

It has a X register of 4 Bits for setting which R register is the Program Counter.

It has a T register of 8 Bits for storing the P register and X register during an Interrupt.

It has a Q register of 1 Bits often for setting an LED on or off.

It has an IE register of 1 Bits for setting and un setting Interrupt Enable during an Interrupt.

It has a Q register of 1 Bits often for setting an LED on or off, which is also one of the 4 outputs.

The 4 Bit N register holds the low order 4 Bits of the Instruction Byte.

The 4 Bit I register holds the high order 4 Bits of the Instruction Byte.

Another fairly good instruction set table listing is in the Intersil CDP1802 datasheet PDF,

at INS-Logo_LG-BW-PC.eps (cosmacelf.com)

What is Computer Programming? :

Historically an offshoot of Mathematics as Computer science, but some practical topics are: Flowchart, Algorithms, Logic Programming, Decomposition (computer science) (like Factorization writing a mathematical object as a product of several factors), Machine Code and Pseudocode, Algorithmic efficiency, Software bug, Cross-platform software (Software portability) (Naming convention (programming)).

A good concise list of the instructions can be found in the Microtutor 2 manual pdf, that I downloaded at: https://groups.io/g/cosmacelf/files/MPM-209%20Microtutor%20II%20Manual.pdf on page 58.

A more in depth lists of the instructions can be found on page 104 to 109, of the COSMAC_VIP_Instruction_Manual_1978.pdf, found as a PDF at: http://bitsavers.org/components/rca/cosmac/COSMAC_VIP_Instruction_Manual_1978.pdf

A thought that comes to my mind is the management of pace.

When people get Math Phobia, they feel that they are to slow,

and that there is no place that they are meant to be and to grow their ability of Math.

It seems to be the same with Coding,

except Coding is unstable compared to Math, as the languages change with time.

Morse code used to be so important, that if needed they slowed down.

Now as a minority use it, after developing the fairly speedy music like skill to convert it in the head,

they do not send slowly, even in bad conditions, unless it is an experimenting learner.

At one time gates were used or an 8 Bit Microprocessor system was used to convert it,

but now gates and 8 Bit are rarely used,

and more effective coding systems are converted on more power computers of awful complexity and instability like the computer languages.

So nowadays speed is an expected norm.

Joseph Weisbecker designed the CDP 1802 at a time when learning to Code 8 Bit was so important,

and there was much less alternatives.

He was also raising 2 Daughters, and put the most I have ever seen into explaining how to code.

Also he created Chip-8, which seems to be a language like Forth, to help build graphics for games on a 34 by 64 monochrome screen.

Consequentially the first ever Woman games programmer was his eldest Daughter called Joyce Weisbecker.

Thus I value trying to learn to code on the CDP 1802.

Eventually to do Morse Code via conversion on a 1802.

The simple things are not only simple, they can be added together with you being more in control for your own life space.

This is the opposite of economic efficiency such as electronics making humans redundant

and so not available to help other humans.

Tyrants such as Putin, seek to consolidate power over others, so it is with computers consolidating there effect on the whole Human race!

Cake and Cable shutdown, to use Satellites to monitor our Internet use and to monitor CCTV feeds and

to monitor via smart phones.

Because Humans tend to allow the wrong People to work on the problems of Natural Law and the impressing people generally of about the God of Nature.

How Computers work:

By organising information, within a practical time, using Mathematics and

high speed Electronic calculation and storage access.

The Mathematics makes an efficient Model of a real world situation, that can usefully manipulated to help someone.

The high speed Electronics calculates and accesses storage at a helpful speed.

The display of the information sometimes relies on tricks of Art to represent real things.

The Mathematics of the programming and coding, is surprisingly achieving,

while fundamentally built on a small amount of some less well known Math,

it is not a small amount of Maths over all.

I would not be surprised if all of Math could help with Programming.

Lee Harts example program 3 for his Membership Card circuit:

Here's the short program:

0000 ORG 0000H 0000 e1 SEX 1. sets the data register as R1.

0001 90 GHI 0. what is in the high part of the data register R0 put into D.

0002 b1 PHI 1. what is in D is put into the high part of R1.

0003 f8 0a LDI. store puts 0A into the D register.

0005 a1 PLO 1. what is in the D register is put into the low part of the data register R1.

0006 6c INP 4. what is on the switches is put into the data register.

0007 64 OUT 4. what is in the data register is displayed.

0008 30 00 BR 0. 00 is put into the program register.

000a 01 store DB 1

Bob Kuczewski bobkuczewski@gmail.com via groups.io 4 Jun 2023, 21:56 to cosmacelf

I was expecting that Lee would add his 16 byte loader to this collection of "Pico Programs".

He may be too modest to brag. :)

Lee's loader was written in collaboration with David and possibly others.

You can find the discussion here: https://groups.io/g/cosmacelf/message/40284

Here's a copy of the code from Lee's post:

; Tiny binary loader for 1802 Elf computer with 256 bytes RAM.

; Receives data on EF3 at 38.4K baud @ 1.79MHz.

Just 16 bytes ; with 256 bytes of RAM (or 17 bytes if over 256 bytes of RAM).

; Max program size is limited by RAM size.

By Lee Hart 2/21/23.

; ; This depends on adding a READ PROTECT switch to disable RAM reads ; and enable reads from a diode-matrix ROM.

Once program is loaded, ; CLEAR, re-enable RAM reads, then RUN to start program at 0000h. ; ; 1st instruction is GHI 0 to load data memory starting at 0000h.

; Change it to GLO 0 to start storing data at 0101h.

Once program ; is loaded, use Front Panel to enter LBR 0101, and RUN it.

0000 ORG 0 ; start at 0000h, with R0=0000h, P=0, X=0 0000 90 GHI 0 ;;; point R2 to 0000h (or GLO 0 for 0101h) ; PHI 2 ;;; add this instruction if over 256 bytes of RAM 0001 a2 PLO 2 ; initialize low byte of R2 if only 256 byte RAM 0002 START: 0002 3e 02 BN3 START ; loop until EF3 pin=0 (Start bit found) 0004 90 GHI 0 ; initialize D=0 to receive a byte 0005 ONE: 0005 ff 00 SMI 0 ; set DF=1 (without changing D) 0007 ZERO: 0007 76 SHRC ; else DF=0 (from D0). shift DF->D7, D0->DF ; STR 2 ;;; 2-cycle NOP \ add to have 6.5 ; STR 2 ;;; 2-cycle NOP | instructions/bit ; NOP ;;; 3-cycle NOP / at 4MHz and 38.4k baud 0008 36 05 B3 ONE ; if EF3 pin=1, go set DF=1 000a 3b 07 BNF ZERO ; if EF3 pin=0 and DF=0, go set DF=0 000c 52 STR 2 ; else 8 bits shifted in, save D 000d 12 INC 2 ; increment to next address 000e 30 02 BR START ; and go to Start ; 11 instructions, 16 bytes. Can be loaded by diode-matrix ROM with ; 1-of-16 decoder. ; ; 3 instructions (1 bit-time) between EF3 samples.

When a Start bit ; is detected, it sets D=0 and DF=1.

The Start and 8 data bits will ; be shifted into D, until the last shift puts the initial 1 in DF ; back into DF again.

The data byte is saved, the address pointer ; incremented, and it loops back to find the next Start bit. ; ; At 1.79MHz, each 2-cycle instruction = 8.94uS. ; At 38.4k baud, each bit = 26.04uS, so 26.04 / 8.94 = 2.91 ; instructions/loop.

Use 3 * 8.94uS = 26.82uS/bit (3% slow).

; ; 4 instructions from START to 1st bit, to read it 33% into the ; bit.

But each bit is read is 3% later, so the 8th bit is ; read at 57%. It is 5 instructions from last EF3 sample, ; so use 2 Stop bits/character.

; ; At 4MHz, each 2-cycle instruction = 4uS. ; At 38.4K baud, each bit = 26.04uS, so 52.1 / 4 = 6.51 ; instructions/loop. Use 6.5 (0.1% fast), add STR 2, STR 2, ; and NOP.

This adds 3 instructions and 3 bytes. 0010 END   Re: A short serial bootloader Lee HartFeb 22 #40284 Success.

I got an email that pointed out that this tiny loader is most useful with an original Elf with only 256 bytes of RAM.

That means the upper half of the address doesn't need to be initialized; which saves 1 byte.

And (drum roll) that gets it down to just 16 bytes. :-)

Here's the scenario:

It's 1976.

You've got an original PE Elf, Elf-II, Super Elf etc. with just 256 bytes of RAM.

It's painful to load programs manually.

And you don't have an EPROM or programmer to put a program in ROM.

How can you automate program loading?

Build a diode-matrix ROM to load this program.

It needs a 1-of-16 decoder (one 4514 or 74LS154, or two 74LS138), 8 resistors, and 48 diodes wired to produce the BINLOAD program.

Change the MP switch from 2-position (RAM write disable/enable) to a 3-position switch (RAM write-disable, RAM read-write-enable, and RAM read-disable + ROM enable) switch.

Flip the MP switch to the RAM read-disable + ROM read-enable position.

CLEAR, then RUN the 1802.

Send it a serial program at 38.4k baud on EF3 (TTL levels, idle high, active low, 1 start, 8 data, 2 stop).

When it finishes loaded, flip the MP switch back to the center RAM read-write-enable position.

CLEAR, then RUN the 1802.

Your downloaded program runs!

The matrix diodes can be normal 1N4148, or LEDs if you like blinken-lights.

A 1-byte addition allows loading into larger RAM (up to the full 64k).

Lee

-- Engineers like to solve problems.

If there are no problems handily available, they will create their own problems.

-- Scott Adams -- Lee Hart, 814 8th Ave N, Sartell MN 56377, www.sunrise-ev.com

-- This email has been checked for viruses by Avast antivirus software. www.avast.com

Thanks Lee!

That's certainly a Pico Program!! :)

From the RCA 1802 Wiki:

This code snippet example is a diagnostic routine that tests ALU (Arithmetic and Logic Unit) Operations.

[47] .. TEST ALU OPS

0000 90 GHI 0 .. SET UP R6

0001 B6 PHI 6

0002 F829 LDI DOIT .. FOR INPUT OF OPCODE

0004 A6 PLO 6

0005 E0 SEX 0 .. (X=0 ALREADY)

0006 6400 OUT 4,00 .. ANNOUNCE US READY

0008 E6 SEX 6 .. NOW X=6

0009 3F09 BN4 * .. WAIT FOR IT

000B 6C INP 4 .. OK, GET IT

000C 64 OUT 4 .. AND ECHO TO DISPLAY

000D 370D B4 * .. WAIT FOR RELEASE

000F F860 LDI #60 .. NOW GET READY FOR

0011 A6 PLO 6 .. FIRST OPERAND

0012 E0 SEX 0 .. SAY SO

0013 6401 OUT 4,01

0015 3F15 BN4 *

0017 E6 SEX 6 .. TAKE IT IN AND ECHO

0018 6C INP 4 .. (TO 0060)

0019 64 OUT 4 .. (ALSO INCREMENT R6)

001A 371A B4 *

001C E0 SEX 0 .. DITTO SECOND OPERAND

001D 6402 OUT 4,02

001F E6 SEX 6

0020 3F20 LOOP: BN4 * .. WAIT FOR IT

0022 6C INP 4 .. GET IT (NOTE: X=6)

0023 64 OUT 4 .. ECHO IT

0024 3724 B4 * .. WAIT FOR RELEASE

0026 26 DEC 6 .. BACK UP R6 TO 0060

0027 26 DEC 6

0028 46 LDA 6 .. GET 1ST OPERAND TO D

0029 C4 DOIT: NOP .. DO OPERATION

002A C4 NOP .. (SPARE)

002B 26 DEC 6 .. BACK TO 0060

002C 56 STR 6 .. OUTPUT RESULT

002D 64 OUT 4 .. (X=6 STILL)

002E 7A REQ .. TURN OFF Q

002F CA0020 LBNZ LOOP .. THEN IF ZERO,

0032 7B SEQ .. TURN IT ON AGAIN

0033 3020 BR LOOP .. REPEAT IN ANY CASE

Note: The above routine presumes that the CDP1802 microprocessor is in an initial reset state (or that it has been set as such prior to executing this code).

Therefore, the program counter (PC) and the X indirect register 'pointer' are both set to 16-bit register R0.

That is why you can output an immediate value, as in the example 'OUT 4,00', because PC and X are both pointing to R0.

The PC is incremented after the opcode instruction byte is retrieved from memory, so it points to the next address when the OUT 4 is executed.

Therefore, it outputs the value in memory pointed to by RX = R0, which is the next immediate byte.

The OUT instruction also increments the X register, which is R0, which is also the PC, so it outputs the immediate value after the OUT and continues program execution at the next instruction address after the immediate value.

This is why you see the routine set X (SEX) to register R6 and R0 as needed.

Also note that, although the OUT opcode increments the RX register, to easily output a section of memory ('buffer'), INP does not.

It stores the value at the address pointed to by RX and into the D 8-bit data byte accumulator, but RX is not modified.

The routine also presumes that OUT 4 will display the value in the CPU system's 8-bit LED or 2-digit hex display, and IN 4 gets the value from the eight toggle switches (or possibly the hex keypad).

The BN4 opcode (loop; * = 'this address'), "branch if the single-bit input EF4 line is lo", is used to test if the momentary 'Input' pushbutton is pressed.

The B4 opcode ('if hi') loop waits for the button to be released. SEQ and REQ turn the single Q line, which is usually attached to an LED, on and off.

The 1802 is a "byte machine", but has 16 16-bit registers, R0-RF (sometimes referred to as 0-F without the 'R' prefix).

To deal with 16-bit register data, the programmer must Get and Put the Hi or Lo values of the registers using the D accumulator as the go-between.

These high and low bytes of the registers are sometimes referred to as Rn.0 (lo) and Rn.1 (hi).

Short Branches are 2-byte opcodes with page-absolute addressing, and a 256-byte address boundary.

Long Branches are 3-byte opcodes with full 16-bit address branching.

This information should make the routine more understandable to any computer programmer who is knowledgeable enough to read "pseudo-code"

and is minimally familiar with assembly and machine language programming.

ChatGPT said this:

The CDP1802 is a CMOS 8-bit microprocessor that was designed for use in aerospace, military, and industrial applications

1. It has 91 easy-to-use instructions1, including four out instructions that are used to output data from the CPU to an external device2.

The out instructions are:

OUT N: Output the contents of the accumulator (D) to the I/O port specified by N (0-7). The I/O port address is formed by appending N to the lower 4 bits of the X register. The instruction takes 2 cycles to execute.

OUTP: Output the contents of the accumulator (D) to the I/O port specified by P (0-15). The I/O port address is formed by appending P to the lower 4 bits of the X register. The instruction takes 2 cycles to execute.

OUTR: Output the contents of the register pair R(0) and R(1) to the I/O port specified by R(2).

The I/O port address is formed by appending R(2) to the lower 4 bits of the X register.

The instruction takes 3 cycles to execute.

OUTI: Output the contents of the memory location pointed by R(0) and R(1) to the I/O port specified by R(2).

The I/O port address is formed by appending R(2) to the lower 4 bits of the X register.

The instruction takes 4 cycles to execute.

I hope this helps you understand the out instructions of the CDP1802.

Here ChatGPT tries again, as I could make sense of the first effort:

The CDP1802 is a CMOS 8-bit microprocessor that was designed for use in aerospace, military, and industrial applications.

It has 91 easy-to-use instructions, including four **out instructions** that are used to output data from the CPU to an external device.

The out instructions are:

- **OUT N**: Output the contents of the accumulator (D) to the I/O port specified by N (0-7). The I/O port address is formed by appending N to the lower 4 bits of the X register. The instruction takes 2 cycles to execute.

 - **OUTP**: Output the contents of the accumulator (D) to the I/O port specified by P (0-15). The I/O port address is formed by appending P to the lower 4 bits of the X register. The instruction takes 2 cycles to execute.

- **OUTR**: Output the contents of the register pair R(0) and R(1) to the I/O port specified by R(2). The I/O port address is formed by appending R(2) to the lower 4 bits of the X register. The instruction takes 3 cycles to execute.

- **OUTI**: Output the contents of the memory location pointed by R(0) and R(1) to the I/O port specified by R(2). The I/O port address is formed by appending R(2) to the lower 4 bits of the X register. The instruction takes 4 cycles to execute. I hope this helps you understand the out instructions of the CDP1802.

Learn more: 1. renesas.com 2. cosmacelf.com 3. scribd.com 1of5 Like Dislike Share More

Thank you very much.

I said:

Can you explain the in instructions?

How do I program a CDP1802?

Stop Responding New topic 0/2000

Feedback DATASHEET - renesas.com https://www.renesas.com/us/en/document/dst/cdp18 

Bing chat said on 2023.7.12:

To the question:

Could you explain the function of the 256 Hexadecimal numbered Instructions of the RCA CDP 1802 Microprocessor?

The RCA CDP 1802 Microprocessor is an 8-bit register-oriented central processing unit (CPU) designed for use as a general-purpose computing or control element in a wide range of stored-program systems or products. The CDP1802 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories12. The CDP 1802 instructions are listed in hexadecimal order as a list of 92 items that cover all of the 256 possible two-digit hexadecimal numbers3.

I hope this helps!

12 squared added to 3 squared is 144+9=153 and 123 in a mirror from underneath looks like 153, and I intend to put this in my blog:

THE MORE I BELIEVE THE MORE I FIND!

For some while I have wondered which of the two microprocessors, the 1802 or the 65816 to invest learning in.

A Google of "stranded" "remote" "data logger" "1802 microprocessor" got many more results, than did "stranded" "remote" "data logger" "65816  microprocessor", that only showed 2 results. This is as I was expecting, as I was thinking about the sort of historical application for those to microprocessors, in the context of the surrounding Human social culture.

Both were designed to be low power consumption, like CMOS gates are, but I noticed that people who were interested in the 6502 legacy and the 1802 legacy, seemed to have differing levels of patience for questions on electronics.

At first I put it down to the smallness of the 1802 fan group, compared to the 6502, but now I put it down to the culture of coping with the isolation of remote data logging environments.

Conversely this Google of "game" "win" "fastest" "6502 microprocessor" got many more results, than did "game" "win" "fastest" "1802  microprocessor", that for which Google gave this message: "It looks like there aren't many great matches for your search".

Confirming for me that patience wears thin in the 6502 camp, compared to the 1802 camp.

For some while I have wondered which of the two microprocessors, the 1802 or the 65816 to invest learning in.

A Google of "stranded" "remote" "data logger" "1802 microprocessor" got many more results, than did "stranded" "remote" "data logger" "65816  microprocessor", that only showed 2 results. This is as I was expecting, as I was thinking about the sort of historical application for those to microprocessors, in the context of the surrounding Human social culture.

Both were designed to be low power consumption, like CMOS gates are, but I noticed that people who were interested in the 6502 legacy and the 1802 legacy, seemed to have differing levels of patience for questions on electronics.

At first I put it down to the smallness of the 1802 fan group, compared to the 6502, but now I put it down to the culture of coping with the isolation of remote data logging environments.

Conversely this Google of "game" "win" "fastest" "6502 microprocessor" got many more results, than did "game" "win" "fastest" "1802  microprocessor", that for which Google gave this message: "It looks like there aren't many great matches for your search".

Confirming for me that patience wears thin in the 6502 camp, compared to the 1802 camp.